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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a lc 2 mos complete 14-bit dac ad7840 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 functional block diagram features complete 14-bit voltage output dac parallel and serial interface capability 80 db signal-to-noise ratio interfaces to high speed dsp processors e.g., adsp-2100, tms32010, tms32020 45 ns min wr pulse width low power C 70 mw typ. operates from 6 5 v supplies general description the ad7840 is a fast, complete 14-bit voltage output d/a con- verter. it consists of a 14-bit dac, 3 v buried zener reference, dac output amplifier and high speed control logic. the part features double-buffered interface logic with a 14-bit input latch and 14-bit dac latch. data is loaded to the input latch in either of two modes, parallel or serial. this data is then transferred to the dac latch under control of an asynchronous ldac signal. a fast data setup time of 21 ns allows direct parallel interfacing to digital signal processors and high speed 16-bit microprocessors. in the serial mode, the maximum serial data clock rate can be as high as 6 mhz. the analog output from the ad7840 provides a bipolar output range of 3 v. the ad7840 is fully specified for dynamic per- formance parameters such as signal-to-noise ratio and harmonic distortion as well as for traditional dc specifications. full power output signals up to 20 khz can be created. the ad7840 is fabricated in linear compatible cmos (lc 2 mos), an advanced, mixed technology process that com- bines precision bipolar circuits with low power cmos logic. the part is available in a 24-pin plastic and hermetic dual-in-line package (dip) and is also packaged in a 28-termi- nal plastic leaded chip carrier (plcc). product highlights 1. complete 14-bit d/a function the ad7840 provides the complete function for creating ac signals and dc voltages to 14-bit accuracy. the part features an on-chip reference, an output buffer amplifier and 14-bit d/a converter. 2. dynamic specifications for dsp users in addition to traditional dc specifications, the ad7840 is specified for ac parameters including signal-to-noise ratio and harmonic distortion. these parameters along with important timing parameters are tested on every device. 3. fast, versatile microprocessor interface the ad7840 is capable of 14-bit parallel and serial interfac- ing. in the parallel mode, data setup times of 21 ns and write pulse widths of 45 ns make the ad7840 compatible with modern 16-bit microprocessors and digital signal processors. in the serial mode, the part features a high data transfer rate of 6 mhz.
rev. b C2C ad7840Cspecifications (v dd = +5 v 6 5%, v ss = C5 v 6 5%, agnd = dgnd = o v, ref in = +3 v, r l = 2 k v , c l = 100 pf. all specifications t min to t max unless othewise noted.) parameter j, a 1 k, b 1 s 1 units test conditions/comments dynamic performance 2 signal to noise ratio 3 (snr) 76 78 76 db min v out = 1 khz sine wave, f sample = 100 khz typically 82 db at +25 c for 0 < v out < 20 khz 4 total harmonic distortion (thd) C78 C80 C78 db max v out = 1 khz sine wave, f sample = 100 khz typically C84 db at +25 c for 0 < v out < 20 khz 4 peak harmonic or spurious noise C78 C80 C78 db max v out = 1 khz sine wave, f sample = 100 khz typically C84 db at +25 c for 0 < v out < 20 khz 4 dc accuracy resolution 14 14 14 bits integral nonlinearity 2 1 2 lsb max differential nonlinearity 0.9 0.9 0.9 lsb max guaranteed monotonic bipolar zero error 10 10 10 lsb max positive full scale error 5 10 10 10 lsb max negative full scale error 5 10 10 10 lsb max reference output 6 ref out @ +25 c 2.99 2.99 2.99 v min 3.01 3.01 3.01 v max ref out tc 60 60 60 ppm/ c max reference load change ( d ref out vs. d i) C1 C1 C1 mv max reference load current change (0C500 m a) reference input reference input range 2.85 2.85 2.85 v min 3 v 5% 3.15 3.15 3.15 v max input current 50 50 50 m a max logic inputs input high voltage, v inh 2.4 2.4 2.4 v min v dd = 5 v 5% input low voltage, v inl 0.8 0.8 0.8 v max v dd = 5 v 5% input current, i in 10 10 10 m a max v in = 0 v to v dd input current ( cs input only) 10 10 10 m a max v in =v ss to v dd input capacitance, c in 7 10 10 10 pf max analog output output voltage range 3 3 3 v nom dc output impedance 0.1 0.1 0.1 w typ short-circuit current 20 20 20 ma typ ac characteristics 7 voltage output settling time settling time to within 1/2 lsb of final value positive full-scale change 4 4 4 m s max typically 2 m s negative full-scale change 4 4 4 m s max typically 2.5 m s digital-to-analog glitch impulse 10 10 10 nv secs typ digital feedthrough 2 2 2 nv secs typ power requirements v dd +5 +5 +5 v nom 5% for specified performance v ss C5 C5 C5 v nom 5% for specified performance i dd 14 14 15 ma max output unloaded, sclk = +5 v. typically 10 ma i ss 6 6 7 ma max output unloaded, sclk = +5 v. typically 4 ma power dissipation 100 100 110 mw max typically 70 mw notes 1 temperature ranges are as follows: j, k versions, 0 c to +70 c; a, b versions, C25 c to +85 c; s version, C55 c to +125 c. 2 v out (pk-pk) = 3 v 3 snr calculation includes distortion and noise components. 4 using external sample-and-hold (see testing the ad7840). 5 measured with respect to ref in and includes bipolar offset error. 6 for capacitive loads greater than 50 pf, a series resistor is required (see internal reference section). 7 sample tested @ +25 c to ensure compliance. specifications subject to change without notice.
ad7840 rev. b C3C ordering guide integral temperature snr nonlinearity package model 1 range (db) (lsb) option 2 ad7840jn 0 c to +70 c 78 min 2 max n-24 ad7840kn 0 c to +70 c 80 min 1 max n-24 ad7840jp 0 c to +70 c 78 min 2 max p-28a ad7840kp 0 c to +70 c 80 min 1 max p-28a ad7840aq C25 c to +85 c 78 min 2 max q-24 ad7840ars C25 c to +85 c 78 min 2 max rs-24 ad7840bq C25 c to +85 c 80 min 1 max q-24 ad7840sq 3 C55 c to +125 c 78 min 2 max q-2 4 notes 1 to order mil-std-883, class b processed parts, add /883b to part number. contact your local sales office for military data sheet and availability. 2 n = plastic dip; p = plastic leaded chip carrier; q = cerdip. 3 this grade will be available to /883b processing only. timing characteristics 1, 2 limit at t min , t max limit at t min , t max parameter (j, k, a, b versions) (s version) units conditions/comments t 1 0 0 ns min cs to wr setup time t 2 0 0 ns min cs to wr hold time t 3 45 50 ns min wr pulse width t 4 21 28 ns min data valid to wr setup time t 5 10 15 ns min data valid to wr hold time t 6 40 40 ns min ldac pulse width t 7 50 50 ns min sync to sclk falling edge t 8 3 150 200 ns min sclk cycle time t 9 30 40 ns min data valid to sclk setup time t 10 75 100 ns min data valid to sclk hold time t 11 75 100 ns min sync to sclk hold time notes 1 timing specifications in bold print are 100% production tested. all other times are sample tested at +25 c to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of 5 v) and timed from a voltage level of 1.6 v. 2 see figures 6 and 8. 3 sclk mark/space ratio is 40/60 to 60/40. specifications subject to change without notice. (v dd = +5 v 6 5%, v ss = C5 v 6 5%, agnd = dgnd = 0 v.) absolute maximum ratings* v dd to agnd . . . . . . . . . . . . . . . . . . . . . . . . . C0.3 v to +7 v v ss to agnd . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v to C7 v agnd to dgnd . . . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v v out to agnd . . . . . . . . . . . . . . . . . . . . . . . . . . . v ss to v dd ref out to agnd . . . . . . . . . . . . . . . . . . . . . . . 0 v to v dd ref in to agnd . . . . . . . . . . . . . . . . C0.3 v to v dd + 0.3 v digital inputs to dgnd . . . . . . . . . . . C0.3 v to v dd + 0.3 v operating temperature range commercial (j, k versions) . . . . . . . . . . . . . . 0 c to +70 c industrial (a, b versions) . . . . . . . . . . . . . . C25 c to +85 c extended (s version) . . . . . . . . . . . . . . . . C55 c to +125 c storage temperature range . . . . . . . . . . . . C65 c to +150 c lead temperature (soldering, 10 sec) . . . . . . . . . . . . +300 c power dissipation (any package) to +75 c . . . . . . . . 450 mw derates above +75 c by . . . . . . . . . . . . . . . . . . . . 10 mw/ c *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7840 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad7840 rev. b C4C pin function description dip pin pin no. mnemonic function 1 cs /serial chip select/serial input. when driven with normal logic levels, it is an active low logic input which is used in conjunction with wr to load parallel data to the input latch. for applications where cs is perma- nently low, an r, c is required for correct power-up (see ldac input). if this input is tied to v ss , it de- fines the ad7840 for serial mode operation. 2 wr/ sync write/frame synchronization input. in the parallel data mode, it is used in conjunction with cs to load parallel data. in the serial mode of operation, this pin functions as a frame synchronization pulse with se- rial data expected after the falling edge of this signal. 3 d13/sdata data bit 13(msb)/serial data. when parallel data is selected, this pin is the d13 input. in serial mode, sdata is the serial data input which is used in conjunction with sync and sclk to transfer serial data to the ad7840 input latch. 4 d12/sclk data bit 12/serial clock. when parallel data is selected, this pin is the d12 input. in the serial mode, it is the serial clock input. serial data bits are latched on the falling edge of sclk when sync is low. 5 d11/format data bit 11/data format. when parallel data is selected, this pin is the d11 input. in serial mode, a logic 1 on this input indicates that the msb is the first valid bit in the serial data stream. a logic 0 indicates that the lsb is the first valid bit (see table i). 6 d10/justify data bit 10/data justification. when parallel data is selected, this pin is the d10 input. in serial mode, this input controls the serial data justification (see table i). 7C11 d9Cd5 data bit 9 to data bit 5. parallel data inputs. 12 dgnd digital ground. ground reference for digital circuitry. 13C16 d4Cd1 data bit 4 to data bit 1. parallel data inputs. 17 d0 data bit 0 (lsb). parallel data input. 18 v dd positive supply, +5 v 5%. 19 agnd analog ground. ground reference for dac, reference and output buffer amplifier. 20 v out analog output voltage. this is the buffer amplifier output voltage. bipolar output range ( 3 v with ref in = +3 v). 21 v ss negative supply voltage, C5 v 5%. 22 ref out voltage reference output. the internal 3 v analog reference is provided at this pin. to operate the ad7840 with internal reference, ref out should be connected to ref in. the external load capability of the reference is 500 m a. 23 ref in voltage reference input. the reference voltage for the dac is applied to this pin. it is internally buffered before being applied to the dac. the nominal reference voltage for correct operation of the ad7840 is 3 v. 24 ldac load dac. logic input. a new word is loaded into the dac latch from the input latch on the falling edge of this signal (see interface logic information section). the ad7840 should be powered-up with ldac high. for applications where ldac is permanently low, an r, c is required for correct power-up (see figure 19). table i. serial data modes
ad7840 rev. b C5C pin configurations dip/ssop plcc for external use, it should he decoupled to agnd with a 200 w resistor in series with a parallel combination of a 10 m f tantalum capacitor and a 0.1 m f ceramic capacitor. figure 2. internal reference external reference in some applications, the user may require a system reference or some other external reference to drive the ad7840 reference in- put. figure 3 shows how the ad586 5 v reference can be con- ditioned to provide the 3 v reference required by the ad7840 ref in. an alternate source of reference voltage for the ad7840 in systems which use both a dac and an adc is to use the ref out voltage of adcs such as the ad7870 and ad7871. a circuit showing this arrangement is shown in figure 20. figure 3. ad586 driving ad7840 ref in d/a section the ad7840 contains a 14-bit voltage mode d/a converter consisting of highly stable thin film resistors and high speed nmos single-pole, double-throw switches. the simplified cir- cuit diagram for the dac section is shown in figure 1. the three msbs of the data word are decoded to drive the seven switches aCg. the 11 lsbs switch an 11-bit r-2r ladder struc- ture. the output voltage from this converter has the same polar- ity as the reference voltage, ref in. the ref in voltage is internally buffered by a unity gain ampli- fier before being applied to the d/a converter and the bipolar bias circuitry. the d/a converter is configured and sealed for a 3 v reference and the device is tested with 3 v applied to ref in. operating the ad7840 at reference voltages outside the 5% tolerance range may result in degraded performance from the part. figure 1. dac ladder structure internal reference the ad7840 has an on-chip temperature compensated buried zener reference (see figure 2) which is factory trimmed to 3 v 10 mv. the reference voltage is provided at the ref out pin. this reference can be used to provide both the reference voltage for the d/a converter and the bipolar bias circuitry. this is achieved by connecting the ref out pin to the ref in pin of the device. the reference voltage can also be used as a reference for other components and is capable of providing up to 500 m a to an ex- ternal load. the maximum recommended capacitance on ref out for normal operation is 50 pf. if the reference is required
ad7840 rev. b C6C op amp section the output from the voltage mode dac is buffered by a noninverting amplifier. internal scaling resistors on the ad7840 configure an output voltage range of 3 v for an input reference voltage of +3 v. the arrangement of these resistors around the output op amp is as shown in figure 1. the buffer amplifier is capable of developing 3 v across a 2 k w and 100 pf load to ground and can produce 6 v peak-to-peak sine wave signals to a frequency of 20 khz. the output is updated on the falling edge of the ldac input. the amplifier settles to within 1/2 lsb of its final value in typically less than 2.5 m s. the small signal (200 mv p-p) bandwidth of the output buffer amplifier is typically 1 mhz. the output noise from the ampli- fier is low with a figure of 30 nv/ ? hz at a frequency of 1 khz. the broadband noise from the amplifier exhibits a typical peak- to-peak figure of 150 m v for a 1 mhz output bandwidth. figure 4 shows a typical plot of noise spectral density versus frequency for the output buffer amplifier and for the on-chip reference. figure 4. noise spectral density vs. frequency transfer function the basic circuit configuration for the ad7840 is shown in fig- ure 5. table ii shows the ideal input code to output voltage re- lationship for this configuration. input coding to the dac is 2s complement with 1 lsb = fs/16,384 = 6 v/16,384 = 366 m v. figure 5. ad7840 basic connection diagram table ii. ideal input/output code table dac latch contents msb lsb analog output, v out * 0 1 1 1 1 1 1 1 1 1 1 1 1 1 +2.999634 v 0 1 1 1 1 1 1 1 1 1 1 1 1 0 +2.999268 v 0 0 0 0 0 0 0 0 0 0 0 0 0 1 +0.000366 v 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 v 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C0.000366 v 1 0 0 0 0 0 0 0 0 0 0 0 0 1 C2.999634 v 1 0 0 0 0 0 0 0 0 0 0 0 0 0 C3 v *assuming ref in = +3 v. the output voltage can be expressed in terms of the input code, n, using the following expression: v out = 2 n refin 16384 - 8192 n + 8191 interface logic information the ad7840 contains two 14-bit latches, an input latch and a dac latch. data can be loaded to the input latch in one of two basic interface formats. the first is a parallel 14-bit wide data word; the second is a serial interface where 16 bits of data are serially clocked into the input latch. in the parallel mode, cs and wr control the loading of data. when the serial data format is selected, data is loaded using the sclk, sync and sdata serial inputs. data is transferred from the input latch to the dac latch under control of the ldac signal. only the data in the dac latch determines the analog output of the ad7840. parallel data format table iii shows the truth table for ad7840 parallel mode op- eration. the ad7840 normally operates with a parallel input data format. in this case, all 14 bits of data (appearing on data inputs d13 (msb) through d0 (lsb)) are loaded to the ad7840 input latch at the same time. cs and wr control the loading of this data. these control signals are level-triggered; therefore, the input latch can be made transparent by holding both signals at a logic low level. input data is latched into the in- put latch on the rising edge of cs or wr . the dac latch is also level triggered. the dac output is nor- mally updated on the falling edge of the ldac signal. however, both latches cannot become transparent at the same time. therefore, if ldac is hardwired low, the part operates as fol- lows; with ldac low and cs and wr high, the dac latch is transparent. when cs and wr go low (with ldac still low), the input latch becomes transparent but the dac latch is dis- abled. when cs or wr return high, the input latch is locked out and the dac latch becomes transparent again and the dac output is updated. the write cycle timing diagram for parallel data is shown in figure 6. figure 7 shows the simplified parallel input control logic for the ad7840.
ad7840 rev. b C7C table iii. parallel mode truth table cs wr ldac function hx h } both latches latched xh h l l h input latch transparent hh l } input latch latched h x l dac latch transparent x h l analog output updated ff l input latch transparent dac latch data transfer inhibited l g l } input latch is latched g l dac latch data transfer occurs x = dont care figure 6. parallel mode timing diagram figure 7. ad7840 simplified parallel input control logic serial data format the serial data format is selected for the ad7840 by connecting the cs /serial line to C5 v. in this case, the wr / sync , d13/sdata, d12/sclk, d11/format and d10/justify pins all assume their serial functions. the unused parallel inputs should not be left unconnected to avoid noise pickup. serial data is loaded to the input latch under control of sclk, sync and sdata. the ad7840 expects a 16-bit stream of serial data on its sdata input. serial data must be valid on the falling edge of sclk. the sync input provides the frame synchroni- zation signal which tells the ad7840 that valid serial data will be available for the next 16 falling edges of sclk. figure 8 shows the timing diagram for serial data format. figure 8. serial mode timing diagram although 16 bits of data are clocked into the ad7840, only 14 bits go into the input latch. therefore, two bits in the stream are dont cares since their value does not affect the input latch data. the order and position in which the ad7840 accepts the 14 bits of input data depends upon the format and justify in- puts. there are four different input data modes which can be chosen (see table i in the pin function description section). the first mode (m1) assumes that the first two bits of the input data stream are dont cares, the third bit is the lsb and the last (or 16th bit) is the msb. this mode is chosen by tying both the format and justify pins to a logic 0. the second mode (m2; format = 0, justify = 1) assumes that the first bit in the data stream is the lsb, the fourteenth bit is the msb and the last two bits are dont cares. the third mode (m3; format= 1, justify 0) assumes that the first two bits in the stream are again dont cares, the third bit is now the msb and the sixteenth bit is the lsb. the final mode (m4; for- mat = 1, justify= 1) assumes that the first bit is the msb, the fourteenth bit is the lsb and the last two bits of the stream are dont cares.
ad7840 rev. b C8C as in the parallel mode, the ldac signal controls the loading of data to the dac latch. normally, data is loaded to the dac latch on the falling edge of ldac . however, if ldac is held low, then serial data is loaded to the dac latch on the sixteenth falling edge of sclk. if ldac goes low during the transfer of serial data to the input latch, no dac latch update takes place on the falling edge of ldac . if ldac stays low until the serial transfer is completed, then the update takes place on the six- teenth falling edge of sclk. if ldac returns high before the serial data transfer is completed, no dac latch update takes place. figure 9 shows the simplified serial input control logic for the ad7840. figure 9. ad7840 simplified serial input control logic ad7840 dynamic specifications the ad7840 is specified and 100% tested for dynamic perfor- mance specifications as well as traditional dc specifications such as integral and differential nonlinearity. these ac specifications are required for the signal processing applications such as speech synthesis, servo control and high speed modems. these applications require information on the dacs effect on the spectral content of the signal it is creating. hence, the param- eters for which the ad7840 is specified include signal-to-noise ratio, harmonic distortion and peak harmonics. these terms are discussed in more detail in the following sections. signal-to-noise ratio (snr) snr is the measured signal-to-noise ratio at the output of the dac. the signal is the rms magnitude of the fundamental. noise is the rms sum of all the nonfundamental signals up to half the sampling frequency (fs/2) excluding dc. snr is depen- dent upon the number of quantization levels used in the digiti- zation process; the more levels, the smaller the quantization noise. the theoretical signal to noise ratio for a sine wave out- put is given by snr = (6.02 n + 1.76) db (1) where n is the number of bits. thus for an ideal 14-bit con- verter, snr = 86 db. figure 10 shows a typical 2048 point fast fourier transform (fft) plot of the ad7840kn with an output frequency of 1 khz and an update rate of 100 khz. the snr obtained from this graph is 81.8 db. it should be noted that the harmonics are taken into account when calculating the snr. figure 10. ad7840 fft plot effective number of bits the formula given in (1) relates the snr to the number of bits. rewriting the formula, as in (2) it is possible to get a measure of performance expressed in effective number of bits (n). n = snr - 1. 7 6 6.02 (2) the effective number of bits for a device can be calculated directly from its measured snr. harmonic distortion harmonic distortion is the ratio of the rms sum of harmonics to the fundamental. for the ad7840, total harmonic distortion (thd) is defined as thd = 20 log v 2 2 + v 3 2 + v 4 2 + v 5 2 + v 6 2 v 1 where v 1 is the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 and v 6 are the rms amplitudes of the second through the sixth harmonic. the thd is also derived from the 2048-point fft plot. peak harmonic or spurious noise peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the dac output spectrum (up to fs/2 and excluding dc) to the rms value of the fundamental. normally, the value of this specification will be determined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor the peak will be a noise peak. testing the ad7840 a simplified diagram of the method used to test the dynamic performance specifications is outlined in figure 11. data is loaded to the ad7840 under control of the microcontroller and associated logic at a 100 khz update rate. the output of the ad7840 is applied to a ninth order, 50 khz, low-pass filter. the output of the filter is in turn applied to a 16-bit accurate digi- tizer. this digitizes the signal and the microcontroller generates an fft plot from which the dynamic performance of the ad7840 can be evaluated.
ad7840 rev. b C9C figure 11. ad7840 dynamic performance test circuit the digitizer sampling is synchronized with the ad7840 update rate to ease fft calculations. the digitizer samples the ad7840 after the output has settled to its new value. therefore, if the digitizer was to sample the output directly it would effec- tively be sampling a dc value each time. as a result, the dynamic performance of the ad7840 would not be measured correctly. using the digitizer directly on the ad7840 output would give better results than the actual performance of the ad7840. us- ing a filter between the dac and the digitizer means that the digitizer samples a continuously moving signal and the true dy- namic performance of the ad7840 is measured. some applications will require improved performance versus fre- quency from the ad7840. in these applications, a simple sample-and-hold circuit such as that outlined in figure 12 will extend the very good performance of the ad7840 to 20 khz. figure 12. sample-and-hold circuit other applications will already have an inherent sample-and- hold function following the ad7840. an example of this type of application is driving a switched-capacitor filter where the up- dating of the dac is synchronized with the switched-capacitor filter. this inherent sample-and-hold function also extends the frequency range performance of the ad7840. performance versus frequency the typical performance plots of figures 13 and 14 show the ad7840s performance over a wide range of input frequencies at an update rate of 100 khz. the plot of figure 13 is without a sample-and-hold on the ad7840 output while the plot of figure 14 is generated with the sample-and-hold circuit of figure 12 on the output. figure 13. performance vs. frequency (no sample-and-hold) figure 14. performance vs. frequency (with sample-and-hold)
ad7840 rev. b C10C microprocessor interfacing the ad7840 logic architecture allows two interfacing options for interfacing the part to microprocessor systems. it offers a 14-bit wide parallel format and a serial format. fast pulse widths and data setup times allow the ad7840 to interface directly to most microprocessors including the dsp processors. suitable interfaces to various microprocessors are shown in figures 15 to 23. parallel interfacing figures 15 to 17 show interfaces to the dsp processors, the adsp-2100, the tms32010 and tms32020. an external timer controls the updating of the ad7840. data is loaded to the ad7840 input latch using the following instructions: adsp-2100: dm(dac) = mr0 tms32010: out dac,d tms32020: out dac,d mr0 = adsp-2100 mr0 register d = data memory address dac = ad7840 address figure 15. ad7840Cadsp-2100 parallel interface figure 16. ad7840Ctms32010 parallel interface figure 17. ad7840Ctms32020 parallel interface some applications may require that the updating of the ad7840 dac latch be controlled by the microprocessor rather than the external timer. one option (for double-buffered interfacing) is to decode the ad7840 ldac from the address bus so that a write operation to the dac latch (at a separate address than the input latch) updates the output. an example of this is shown in the 8086 interface of figure 18. note that connecting the ldac input to the cs input will not load the dac latch cor- rectly since both latches cannot he transparent at the same time. ad7840C8086 interface figure 18 shows an interface between the ad7840 and the 8086 microprocessor. for this interface, the ldac input is derived from a decoded address. if the least significant address line, a0, is decoded then the input latch and the dac latch can reside at consecutive addresses. a move instruction loads the input latch while a second move instruction updates the dac latch and the ad7840 output. the move instruction to load a data word wxyz to the input latch is as follows: mov dac,#yzwx dac = ad7840 address figure 18. ad7840C8086 parallel interface
ad7840 rev. b C11C ad7840C68000 interface an interface between the ad7840 and the 68000 microproces- sor is shown in figure 19. in this interface example, the ldac input is hardwired low. as a result the dac latch and analog output are updated on the rising edge of wr . a single move instruction, therefore, loads the input latch and updates the output. move.w d0,$dac d0 = 68000 d0 register dac = ad7840 address figure 19. ad7840Cmc68000 parallel interface serial interfacing figures 20 to 23 show the ad7840 configured for serial inter- facing with the cs input hardwired to C5 v. the parallel bus is not activated during serial communication with the ad7840. ad7840Cadsp-2101/adsp-2102 serial interface figure 20 shows a serial interface between the ad7840 and the adsp-2101/adsp-2102 dsp processor. also included in the interface is the ad7870, a 12-bit a/d converter. an interface such as this is suitable for modem and other applications which have a dac and an adc in serial communication with a microprocessor. the interface uses just one of the two serial ports of the adsp-2101/adsp-2102. conversion is initiated on the ad7870 at a fixed sample rate (e.g., 9.6 khz) which is provided by a timer or clock recovery circuitry. while communication takes place between the adc and the adsp-2101/ adsp-2102, the ad7870 sstrb line is low. this sstrb line is used to provide a frame synchronization pulse for the ad7840 sync and adsp-2101/adsp-2102 tfs lines. this means that com- munication between the processor and the ad7840 can only take place while the ad7870 is communicating with the processor. this arrangement is desirable in systems such as modems where the dac and adc communication should be synchronous. the use of the ad7870 sclk for the ad7840 sclk and adsp-2101/adsp-2102 sclk means that only one serial port of the processor is used. the serial clock for the ad7870 must be set for continuous clock for correct operation of this interface. data from the adsp-2101/adsp-2102 is valid on the falling edge of sclk. the ldac input of the ad7840 is permanently low so the update of the dac latch and analog output takes place on the sixteenth falling edge of sclk (with sync low). the format pin of the ad7840 must be tied to +5 v and the justify pin tied to dgnd for this interface to operate correctly. figure 20. complete dac/adc serial interface ad7840Cdsp56000 serial interface a serial interface between the ad7840 and the dsp56000 is shown in figure 21. the dsp56000 is configured for normal mode synchronous operation with gated clock. it is also set up for a 16-bit word with sck and sc2 as outputs and the fsl control bit set to a 0. sck is internally generated on the dsp56000 and applied to the ad7840 sclk input. data from the dsp56000 is valid on the falling edge of sck. the sc2 output provides the framing pulse for valid data. this line must be inverted before being applied to the sync input of the ad7840. the ldac input of the ad7840 is connected to dgnd so the update of the dac latch takes place on the sixteenth falling edge of sclk. as with the previous interface, the format pin of the ad7840 must be tied to +5 v and the justify pin tied to dgnd. figure 21. ad7840Cdsp56000 serial interface
ad7840 rev. b C12C ad7840Ctms32020 serial interface figure 22 shows a serial interface between the ad7840 and the tms32020 dsp processor. in this interface, the clkx and fsx pin of the tms32020 are generated from the clock/timer circuitry. the same clock/timer circuitry generates the ldac signal of the ad7840 to synchronize the update of the output with the serial transmission. the fsx pin of the tms32020 must be configured as an input. data from the tms32020 is valid on the falling edge of clkx. once again, the format pin of the ad7840 must be tied to +5 v while the justify pin must be tied to dgnd. figure 22. ad7840Ctms32020 serial interface ad7840Cnec7720 serial interface a serial interface between the ad7840 and the nec7720 is shown in figure 23. the serial clock must be inverted before being applied to the ad7840 sclk input because data from the processor is valid on the rising edge of sck. the nec7720 is programmed for the lsb to be the first bit in the serial data stream. therefore, the ad7840 is set up with the format pin tied to dgnd and the justify pin tied to +5 v. figure 23. ad7840Cnec7720 serial interface applying the ad7840 good printed circuit board layout is as important as the overall circuit design itself in achieving high speed converter perfor- mance. the ad7840 works on an lsb size of 366 m v. there- fore, the designer must be conscious of minimizing noise in both the converter itself and in the surrounding circuitry. switching mode power supplies are not recommended as the switching spikes can feed through to the on-chip amplifier. other causes of concern are ground loops and digital feedthrough from mi- croprocessors. these are factors which influence any high per- formance converter, and a proper pcb layout which minimizes these effects is essential for best performance. layout hints ensure that the layout for the printed circuit board has the digi- tal and analog lines separated as much as possible. take care not to run any digital track alongside an analog signal track. es- tablish a single point analog ground (star ground) separate from the logic system ground. place this star ground as close as pos- sible to the ad7840 as shown in figure 24. connect all analog grounds to this star ground and also connect the ad7840 dgnd pin to this ground. do not connect any other digital grounds to this analog ground point. figure 24. power supply grounding practice low impedance analog and digital power supply common re- turns are essential to low noise operation of high performance converters. therefore, the foil width for these tracks should be kept as wide as possible. the use of ground planes minimizes impedance paths and also guards the analog circuitry from digi- tal noise. the circuit layouts of figures 27 and 28 have both analog and digital ground planes which are kept separated and only joined at the star ground close to the ad7840. noise keep the signal leads on the v out signal and the signal return leads to agnd as short as possible to minimize noise coupling. in applications where this is not possible, use a shielded cable between the dac output and its destination. reduce the ground circuit impedance as much as possible since any poten- tial difference in grounds between the dac and its destination device appears as an error voltage in series with the dac output.
ad7840 rev. b C13C data acquisition board figure 25 shows the ad7840 in a data acquisition circuit. the corresponding printed circuit board (pcb) layout and silkscreen are shown in figures 26 to 28. the board layout has three inter- face ports: one serial and two parallel. one of the parallel ports is directly compatible with the adsp-2100 evaluation board expansion connector. some systems will require the addition of a re-construction filter on the output of the ad7840 to complete the data acquisition system. there is a component grid provided near the analog output on the pcb which may be used for such a filter or any other output conditioning circuitry. to facilitate this option, there is a shorting plug (labeled lk1 on the pcb) on the analog output track. if this shorting plug is used, the analog output connects to the output of the ad7840; otherwise this shorting plug can be omitted and a wire link used to connect the analog output to the pcb component grid. the board also contains a simple sample-and-hold circuit which can be used on the output of the ad7840 to extend the very good performance of the ad7840 over a wider frequency range. a second wire link (labelled lk2 on the pcb) connects v out (skt1) to either the output of this sample-and-hold circuit or directly to the output of the ad7840. interface connections there are two parallel connectors, labeled skt4 and skt6, and one serial connector, labeled skt5. a shorting plug option (lk8 in figure 25) on the ad7840 cs /serial input config- ures the dac for the appropriate interface (see pin function description). skt6 is a 96-contact (3-row) eurocard connector which is di- rectly compatible with the adsp-2100 evaluation board proto- type expansion connector. the expansion connector on the adsp-2100 has eight decoded chip enable outputs labeled ece1 to ece8 . ece6 is used to drive the ad7840 cs input on the data acquisition board. to avoid selecting on-board sockets at the same time, lk6 on the adsp-2100 board must be removed. the ad7840 and adsp-2100 data lines are aligned for left justified data transfer. skt4 is a 26-way (2-row) idc connector. this connector con- tains the same signal contacts as skt6 and in addition contains decoded r/ w and strb inputs which are necessary for tms32020 interfacing. this decoded wr can be selected via lk4. the pinout for this connector is shown in figure 29. skt5 is a nine-way d-type connector which is meant for serial interfacing only. the evaluation board has the facility to invert sync line via lk7. this is necessary for serial interfacing be- tween the ad7840 and dsp processors such as the dsp56000. the skt5 pinout is shown in figure 30. skt1, skt2 and skt3 are three bnc connectors which pro- vide connections for the analog output, the ldac input and an external reference input. the use of an external reference is op- tional; the shorting plug (lk3) connects the ref in pin to ei- ther this external reference or to the ad7840s own internal reference. wire links lk5 and lk6 connect the d11 and d10 inputs to the data lines for parallel operation. in the serial mode, these links allow the user to select the required format and justifica- tion for serial data (see table i). power supply connections the pcb requires two analog power supplies and one 5 v digi- tal supply. connections to the analog supplies are made directly to the pcb as shown on the silkscreen in figure 26. the con- nections are labelled v+ and vC and the range for both of these supplies is 12 v to 15 v. connection to the 5 v digital supply is made through any of the connectors (skt4 to skt6). the C5 v analog supply required by the ad7840 is generated from a voltage regulator on the vC power supply input (ic5 in figure 25). shorting plug options there are eight shorting plug options which must be set before using the board. these are outlined below: lk1 connects the analog output to skt1. the analog output may also be connected to a component grid for signal conditioning. lk2 selects either the ad7840 v out or the sample-and- hold output. lk3 selects either the internal or external reference. lk4 selects the decoded r/ w and strb inputs for tms32020 interfacing. lk5 configures the d11/format input. lk6 configures the d10/justify input. lk7 selects either the inverted or noninverted sync . lk8 selects either parallel or serial interfacing. component list ic1 ad7840 digital-to-analog converter ic2 ad711 op amp ic3 adg201hs high speed switch ic4 74hc221 monostable ic5 79l05 voltage regulator ic6 74hc02 c1, c3, c5, c7, c11, c13, c15, c17 10 m f capacitors c2, c4, c6, c8, c12, c14, c16, c18 0.1 m f capacitors c9 330 pf capacitor c10 68 pf capacitor r1, r2 2.2 k w resistors r3 15 k w resistor rp1, rp2 100 k w resistor packs lk1, lk2, lk3, lk4, lk5, lk6, lk7, lk8 shorting plugs skt1, skt2, skt3 bnc sockets skt4 26-contact (2-row) idc connector skt5 9-contact d-type connector skt6 96-contact (3-row) eurocard connector
ad7840 rev. b C14C figure 25. data acquisition circuit using the ad7840 figure 26. pcb silkscreen for figure 25
ad7840 rev. b C15C figure 27. pcb component side layout for figure 25 figure 28. pcb solder side layout for figure 25
ad7840 rev. b C16C outline dimensions dimensions shown in inches and (mm). plastic dip (n-24) ceramic dip (d-24a) cerdip (q-24) plcc (p-28a) c1259C10C2/89 printed in u.s.a. figure 29. skt4, idc connector pinout figure 30. skt5, d-type connector pinout

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